Martin Strassburg (ams-OSRAM Group)
IPCEI ME/CT – Shaping the Future of Microelectronics Innovation in Europe

Thomas Krivec (AT&S)
IC Substrates & Advanced Packaging Technologies – Key to the Computing Systems
of the Future

Klaus Pressel / Vesna Müller / Gunther Mack (Infineon)
Impact of PreAssembly and Failure Analysis in IPCEI ME/CT

Przemek Gromala (Bosch)
Digital Twin – Challenges and Opportunities in IPCEI ME/CT

Horst Theuss / Walter Hartner (Infineon)
Advanced Requirements for High Frequency Fan-Out WLP

Klaus Pressel (Infineon) and Steffen Kröhnert (ESPAT-Consulting)
Time for Q & A

Abstract

The IPCEI ME/CT is the second “Important Project of Common European Interest” dedicated to the European Microelectronics Ecosystem. This project enables national governments to offer public support to the project’s partners for innovative research and development, as well as investment in the first industrial deployment (FID). In the first part of this special session, Martin Strassburg (ams-Osram) from the IPCEI ME/CT Facilitation Group will introduce the project. The IPCEI ME/CT partners Infineon, Bosch, and AT&S will then present examples of their research and development. This will include innovations in assembly and ackaging technologies for fan-out WLP technology, the importance of preassembly and failure analysis, IC laminate substrates, as well as challenges and opportunities for digital twin technologies.

Speakers

Geert Van Steenberge (imec and Ghent University, Belgium): Need for Wafer-level Packaging Solutions within the Horizon Europe Project PUNCH
Konstantin Morozov (Innolume, Germany): A Foundry Process for Micro-transfer-printing of Semiconductor Optical Amplifiers
Marius Adler (Fraunhofer-IZM, Germany): Fan-out Wafer-level Packaging for Dense Integration of Photonic and Electronic ICs
Jef Van Asch (imec and Ghent University, Belgium): Low-loss Optical Coupling from PICs to an Optical Redistribution Layer

Abstract

Today, despite the use of complex photonic integrated circuits (PICs), the fabrication of a complete optical device still requires a large amount of sequential assembly steps. Integration of PICs, electronic interface circuits, III-V optical gain elements and fiber attachment parts is still based on manual processes on the level of individual devices, limiting scalability and cost efficiency.

To reduce the packaging cost and reach the full potential of integrated photonics, a more disruptive approach is required, shifting complexity from sequential assembly on device level to parallelized planar fabrication on substrate- or wafer-level. Within the Horizon Europe project PUNCH, semiconductor packaging technology compatible with high-volume manufacturing is leveraged for providing full thermal, electrical, and optical packaging solutions. While PUNCH revolves around ultra-dynamic photonic components (such as optical switches), the packaging solutions are generic and have a wide application potential.

The development of a III-V foundry process for micro-transfer-printing compatible semiconductor optical amplifiers enables lossless optical switching on a silicon photonics platform. Custom designed electronic ICs to actuate, control, and power-monitor scaled switch fabrics are densely integrated with the photonic ICs into a heterogeneous fanout wafer-level package (FOWLP), processed on a 200 mm reconstructed wafer platform. In addition, the optical interfacing to the photonic ICs is accomplished using an optical redistribution layer, providing an optical fanout and allowing for a scalable optical fiber packaging solution.

Within this special session, the above-described emerging photonics packaging technologies will be presented, along with the experimental results obtained within the PUNCH project.

Increasing digitalization represents both an opportunity and a challenge for climate protection and resource conservation. While intelligent control of devices, systems, processes, and networks significantly contributes to saving energy in many areas, the progressive spread of information and communication technology (ICT) continues to increase the consumption of energy and resources. Considerable change is necessary in microelectronics and power electronics – both in design and manufacturing. The Research Fab Microelectronics Germany (FMD) has established the “Green ICT @ FMD” competence center to implement the German government’s Green ICT mission. The aim is to promote the sustainable development of ICT based on FMD services, structures, and expertise for application-oriented research in microelectronics. The work of the competence center is not limited to technological research but attempts to initiate a paradigm shift. It involves beside others also the offer for education, training and qualification for beginners as well as specialists.

The course explains the education program and enables the opportunity for industry to give hints and remarks according to the curriculum.

The project is funded by the Federal Ministry of Education and Research, the authors and all representatives of the 13 member institutes of the FMD are grateful for the support.

Eric Fribourg-Blanc (Chips JU), recorded presentation
EU Chips Act – The Role of Chips JU, Pilot Lines, Learnings and what’s next after Pack4EU

Steffen Kröhnert (ESPAT-Consulting/ SEMI Europe)
Packaging in Europe – Growing or Vanishing / Pack4EU Project Results

Gabriela Pereira, Vishal Saroha (YOLE Group)
Summary of the Markét Analysis done for the Pack4EU Project

Elisabeth Steimetz (EPoSS/ VDI-VDE-IT)
Chips Act – Pillar 1: Lab to Fab Accelerator Initiative for Advanced Packaging Made in Europe

Panel Discussion
The Future of Packaging in Europe

Abstract

No digitalization without chips, and no chips without package. Packaging is becoming a product differentiator, and the increasing complexity moves collaborative Chip-Package-Board-System ­co-design in the focus. Through initiatives and the respective funding instruments like IPCEI and the EU CHIPS ACT, the European Union aims to reach its target to increase its global semiconductor market share to 20 % by 2030. But what’s about Electronics Packaging, Assembly and Test? The worldwide manufacturing share in Europe today is only 3 %. Will the majority of wafers ­produced in Europe still be shipped to Asia for Packaging, Assembly and Test in 2030 too? The Horizon-Chips-JU-CSA “Pack4EU” project, started in July 2023 and concluded in June 2024,
has identified the gaps between DEMAND and OFFER in Europe and worked out a set of policy ­recommendations to the European Commission to close those gaps. The project results, the ­“Pan-European Network for Advanced Packaging made in Europe” including the “Packaging Expert Group” to be established will be discussed.

Quantum computing is expected to revolutionize the traditional way of numerical problem solving. Quantum computers have the potential to solve certain problems exponentially faster than classical computers that opens new significant opportunities and challenges, for example, in data security, physical/chemical simulations (e.g. discovery of new materials or drugs), and large-scale data analyses, just to name a few important fields of application. However, the promise of quantum computing lies not only in its potential for computational speed and power, but also in its ability to tackle problems at levels of complexity that are currently not possible with classical methods.

Unlike classical semiconductor chips that rely on binary logic gates, quantum chips harness the principles of quantum mechanics to process information in fundamentally different ways. Despite the many fundamental differences between quantum and semiconductor computers, there are many similarities in their fabrication techniques, however. In this Special Session on Qunatum Chips and Packaging, we explore some of the key aspects of quantum chips and their packaging, highlighting the challenges and advancements in this neighboring field of technology.

Speaker #1: Juha Hassel, VP of Engineering, IQM Quantum computers

Title: High-quality superconducting chips for scalable quantum computing

Abstract: An overview of superconducting quantum computing technology at IQM is presented. The focus will be in the requirements set by the technology to the chip fabrication and describing IQM’s fabrication facility dedicated to the production of quantum processing units.

Contact: juha.hassel@meetiqm.com

Speaker #2: Prof. Mika Prunnila, Chief Research Officer, Co-founder of SemiQon

Title: Custom CMOS Platform for Quantum Devices

Abstract:  Customized CMOS circuitry operating at cryogenic temperatures – cryo-CMOS – is considered to be the key technology for creating a general and flexible cryogenic interfacing and data processing layer for cryo-enabled classical and quantum applications. Small cryo-CMOS transistors where multiple gates confine electrons to tiny pockets forming quantum dots can be also used as qubits. An overview of SemiQon’s approach of using integrated quantum and classical cryo-CMOS for quantum chips is presented.

Contact: mika.prunnila@semiqon.tech

Speaker #3: Jean Charbonnier, R&D Project Leader, CEA Leti

Title: 3D integration for quantum applications

Abstract: Superconducting 3D key enabling technologies are now ready for the scale up, and their compatibility with solid state qubit devices needs to be explored. This talk will cover the main drivers of 3D integration in microelectronic systems and explore the interconnect panel for cryo applications, starting with superconducting routing and via technology, bumping and assembly processes, and a new innovative approach to low pitch superconductive bonding.

Biography: M’19, is graduated from National School of Physics of Grenoble in 2001 and obtained his PhD degree in crystallography from University Joseph Fourier of Grenoble in 2006. He joined the 3D wafer level packaging group of CEA-Leti in 2008. He has been working for more than 15 years with Through Silicon Vias, 3D interconnections and silicon interposers technology. His research interests include High Performance computing, Silicon Photonics Interposer as well as cryo-packaging for Quantum architecture applications. He is currently in charge of coordinating the High-Density 3D Integration group within the 3D Packaging Laboratory of CEA-Leti.

Speaker #4: Jarno Järvinen, Research and Development Scientist, Bluefors

Title: “Cryogenic Wafer Probing”

Abstract: Quantum computing solutions typically require operating temperatures near absolute zero, necessitating specialized cooling and testing methods beyond those used in the conventional semiconductor industry. One of the uses is cryogenic wafer-level testing, crucial for scaling up quantum chip production. This overview will highlight the established cooling techniques to achieve millikelvin temperatures, and provides an example of a cryogenic wafer-level testing solution.

Biography: Jarno Järvinen is a Research and Development Scientist at Bluefors. He completed a PhD in Physics in 2006 at the University of Turku (Finland) and continued as a post-doctoral researcher at Cornell University (USA), Institut Néel (France) and University of Turku, where he also received Adjunct Professor title. He has published 42 scientific publications in the field of quantum gases and solids and is currently focusing on R&D for Bluefors’ Cryogenic Wafer Prober.

Contact: jarno.jarvinen@bluefors.com

Recent Findings at the IEEE EPS Global Education and Workforce Development Workshops

Prof. Jeffrey C. Suhling
Auburn University, USA

Abstract
The semiconductor and packaging industries are experiencing unparalleled growth due large demand in several high-tech areas including artificial intelligence, electrification of transportation, digital manufacturing, data centers, mobile devices, hybrid flexible electronics, virtual reality, and photonics and MEMS.  This has led to government “Chips Act” funding programs coupled with industry investments across the globe in new fabs and packaging infrastructure.  To support this growth, it will be necessary to find the qualified employees at all levels including the engineers, scientists, technicians, and operators needed to support research, design, and production advanced electronic products.  Over the past two years, a series of Education and Workforce Development panels have been held at the flagship ESTC, EPTC, and ECTC conferences of the IEEE Electronics Packaging Society in Europe, Asia, and the USA.  In this presentation, a summary will be given of the findings of these panels including projected workforce needs and challenges facing the industry, methods for attracting and training university-level students, and novel tactics needed in the future for education and training in the semiconductor packaging field.

Shortage of Skilled Workers and the Need for Microelectronics Specialists

Prof. M. Petzold
Fraunhofer IMWS Halle

Abstract
In the coming years, intel plans to build a new semiconductor production facility at the absolute cutting edge of technology in Magdeburg, Germany. The number of employees will be 3,000, divided into around 2,100 technicians (70%), 750 engineers (25%) and 150 management positions (5%). In particular, the recruitment, training and further education of the 2,100 technicians required for the Magdeburg site alone is currently a big challenge.  The problem is further exacerbated by the shortage of skilled workers and the need for microelectronics specialists also at other locations in Germany. Therefore, new comprehensive national concepts and strategies for winning young talent and for adapted vocational training and education are urgently required.

Skills-Based Education and Training Approach

Prof. DHC Paul Svasta, Ph.D
National University of Science and Technology POLITEHNICA  Bucharest, Romania

Abstract
Currently, the educational process in the formation of the workforce, necessary for the microelectronics/electronics industry, faces some difficulties generated by a proper understanding by students of the symbiosis between the theoretical aspects and those present in the engineering profession. We can even assume the existence of a gap between the academic approach and the industrial reality. The situation gets complicated especially in electronic packaging when the package must meet the functional requirements determined by the specifics of the application. However, these requirements are not only electrical but also include many non-electrical requirements (eg mechanical, thermal, etc.).

Accordingly with the mentioned context, an approach that has proven its viability represents  the evaluation and certification, in a competition, of the knowledge of students from the academic environment with focus on  electronics packaging topics. These competitions bring together: students who have to solve the subject prepared by professionals from the industry assisted by teaching staff from academia..

The presentation will highlight aspects of the TIE (Technologies of Interconnection in Electronics) event, www.tie.ro. TIE represents a well-established platform in shaping and validating the skills for the future workforce.

The Need for University Graduates as Microelectronics Specialists

Prof. K.-J. Wolter
TU Dresden, IAVT

Abstract
The presentation highlights the current situation with the increasing need for university graduates as microelectronics specialist. New settlements in the high-tech industry require excellently trained graduates in electrical engineering, microelectronics, computer science and materials science. On the other hand, the number of electrical engineering graduates in particular has decreased in recent years across Germany. In addition, many students drop out of their studies. Numbers will be given in detail. This creates a discrepancy between the future need for microelectronics specialists in high-tech companies and the number of graduates. The discussion is intended to draw attention to this problem and to show ways to increase the attractiveness of technical subjects.