ESTC 2024
Keynotes
Wednesday, 11/Sept/2024, 1:45pm – 2:30pm
A Vision for Modular, Ubiquitous and Scalable Compute Systems
Bernd Waidhas
Principal Engineer, Silicon Packaging Architecture, Intel
Bernd joined Intel in 2011, after starting his business career at Siemens Semiconductors and its later spinoff, Infineon, in 1996. Throughout his career, he has held various roles in mobile phone device packaging development and system co-optimization, collaborating with major customers. His key contributions include the introduction of eWLB and flip chip & wire bond stacked die FBGAs.
Currently, Bernd is part of Intel’s Technology Enablement Group in Munich, focusing on packaging technologies for heterogeneous integration across multiple Intel business units. He holds a master’s degree in electrical engineering from the Technical University of Dresden and serves as a committee member for the Semi Europe 3D & Systems Summit Conference.
Abstract:
Tomorrow’s compute systems will be dictated by domain specific solutions that optimize system performance with affordability. Three key thrusts to enable modular and ubiquitous manufacturing scalability include i) utilization of hybrid bond interconnect scaling, ii) smart system expansion and connectivity, with iii) advanced memory integration. The combination of these elements enable significant performance scaling, removing bandwidth limitations; yet, there are still challenges regarding interface design, test, inspection, and system-level power and thermal control.
Electronics Integration: Challenges in Computed Tomography Scanners
Dr. Michael Hosemann
Head of Digital Electronics at Healthineers Computed Tomography Detector Center, Siemens
Dr. Michael Hosemann is the Head of Digital Electronics at Siemens Healthineers Computed Tomography Detector Center. This spans a range from front-end mixed-signal ASIC development via PCB design, firmware development for ASIC control, data processing to wireless data transmission. Michael did his Diplomingenieur and doctorate degrees at Technische Universität Dresden. Before joining Siemens Healthineers he worked for a variety of companies in Cambridge, UK and Germany, mainly designing wireless and medical systems.
Abstract:
Medical devices pose a large spectrum of challenges for integration of electronics components.
This talk highlights some of those challenges based on the world’s first photon-counting computed tomography scanner, Siemens Healthinneers’ Naeotom Alpha. Examples include gap-less 3D assembly of detector ASICs to handling measurement data in excess of 500Gbit/s.
Challenges and Opportunities of Semiconductor Packaging in the Chiplet Era
Dr. Yasumitsu Orii
Senior Managing Executive Officer in 3D Assembly Division, Rapidus Corporation
Dr. Yasumitsu Orii joined IBM Japan in 1986, was a pioneering figure in Flip Chip organic packages, enhancing performance and miniaturization in servers, laptops, and HDDs. With Moore’s Law limitations, packaging technology gains significance for next-gen servers. Yasumitsu led innovations such as flip chip on FPC for HDDs and developed C2 technology for low-cost flip chip bonding in consumer electronics, licensed to a Taiwanese firm. At IBM Research Tokyo, he spearheaded projects on 3D-IC and Neuromorphic Computing. After leaving IBM in 2014, he joined NAGASE & CO., LTD., launching material informatics software as a service. He left NAGASE and in December 2022 and joined Rapidus Corporation, where he now serves as Senior Managing Executive Officer in the 3D Assembly Division.
Abstract:
Splitting a System-on-Chip (SoC) chip into individual chips (chiplets) by function brings improved yields, shorter design, development cycles, and cost reduction. However, moving from monolithic chips to chiplets brings forth new challenges in high-density interconnects, thermal management, and testing. Additionally, the packaging structures are becoming more complex, resulting in increased design complexity. To address these challenges, the entire industry should promote the integration of front-end and back-end processes and establish a chiplet ecosystem.
CHIPS -NAPMP: Overview and Next Steps
George Orji
George Orji is the Deputy Director of CHIPS NAPMP, within CHIPS R&D Office. Prior to this role, he was a Senior Program Advisor in the CHIPS R&D Office, and before then a Program Analyst in the NIST Program Coordination Office, in the Office of the NIST Director. In that role, he provided technical program and policy analysis, worked with line organizations and other staff offices on planning NIST-level strategies, program evaluation, policy coordination, budget and program initiatives, including early CHIPS Act implementation planning.
He spent more than 15 years in the NIST Labs as a project leader and mechanical engineer in the Physical Measurement, and Manufacturing Engineering Laboratories, where he led projects on nanoscale dimensional metrology, probe-based instrument and measurement methods development, uncertainty analysis, and standards development. He received his PhD in mechanical engineering from the University of North Carolina at Charlotte and is a Senior Member of both IEEE and SPIE.
List of publications/patents:
https://www.nist.gov/people/ndubuisi-george-orji
Abstract:
Friday, 13/Sept/2024, 1:45pm – 2:10pm
Invited Speaker
Accelerating the AI economy through Heterogeneous Integration
Dr. CP Hung
Dr. CP Hung currently holds the position of Vice President, Corporate R&D, at ASE Group. Based in Taiwan, he leads teams responsible for next-generation product development featuring integrated technologies, as well as a broad range of advanced chip, package, and system integration solutions across multiple ASE and USI Sites.
During his tenure, Dr. Hung has performed a variety of management roles at ASE, including VP of Corporate Design, VP of Central Engineering & Business Development and VP of Logistic Services Integration. He holds 187 patents encompassing IC packaging structure, process, substrate and characterization technology, and has published over 109 conference and journal papers. Dr. Hung became Co-Chair of the SEMICON Taiwan Packaging & Test Committee in 2021, after serving as Chair since 2013. He was elected to the IEEE EPS board of governors since 2019.
Abstract
Advanced packages deliver the highest density interconnect between chiplet and memory, and are pivotal to enabling heterogeneous integration technologies for ultrahigh performance module and system.
During his keynote, Dr. CP Hung will explore structural variations, platform differences, and developing milestones for Fan-Out, 2.5D and 3D IC advanced packages with new generation silicon photonics for applications across automotive, edge computing, AI server, and data center.
